Recently, my book entitled “Synchronization in Digital Communication Systems” was published by Cambridge University Press. As I mentioned in its preface, my fellow engineers and I have spent a lot of time on designing, debugging and testing the receiver blocks that are related to synchronization. In this blog, I will provide a summary of the projects that I was involved in my career, and during which I learned synchronization techniques. I will also describe how these techniques were used to solve problems that occurred in design and implementation of modems and communication systems.
In August 1984, after receiving my Ph.D degree from Northeastern University, I joined Codex Corporation working under Dr. Shahid Qureshi, then senior director of the research and advanced development department at Codex. The first project that I worked on was to develop an echo-cancellation modem based on the new CCITT V.32 standard.
In late 1984, Shahid asked me to look into how to compensate for possible far-end echo, or far echo, phase roll. I was involved in the analysis, design and lab testing of this technology. It was shown to be essential for echo cancellation modems over international internetwork connections and became a standard feature of the Codex V. 32 modem.
The central component of far-echo phase-roll compensation is digital phase locked loop (DPLL). It was my first exposure to DPLL and the knowledge gained was invaluable in my later work related to synchronization. My understanding of PLLs is presented in Chapter 4 and the basics of echo cancellation modem are introduced in Section 7.7.1 of this book.
It was my first exposure to DPLL and the knowledge gained was invaluable
In echo cancellation modems, it is necessary to convert the rate of echo-cancelled samples, which are synchronous to the local transmitter symbol rate, to be synchronous to the received signal symbol rate. Originally, such a conversion was done by analog means. In early 1985, Shahid wrote a technical memo which proposed to use digital interpolation to perform such rate conversions, instead using a pair of DAC/ADC in a V.32 modem to reduce the analog component count.
At that time, the theory and realization of digital rate conversion had been well studied and understood. The main difficulty was how to implement it with the limited available processing resources. By carefully designing and coding, and by reducing the processor cycles and program memory for other functions, my design was able to perform necessary resampling functions while still fitting in the available processor cycles and memory. It was later implemented in the final product.
In 1986, the Codex V.32 modem employing this digital resampling technology was introduced to the market. It was probably the first commercial modem product. The same implementation was then used in the later generations of Codex modems. Later, it was introduced to Rockwell International as a part of technology transfer from Codex. A patent application based on this technology was filed in 1987, and a paper describing this technology was published in 1993.
The principles of digital sampling and the various techniques for performing it are presented in detail in Chapter 7 of the book.
In late 1990s, I worked on network clock synchronization between different entities. To reduce the overhead, we proposed to transmit the information for synchronization over a packet data network, rather than a dedicated synchronous subchannel, but packet data transmission introduced unavoidable time-varying delay. The synchronization block design was based on the analysis of PLLs with additional loop delays that we learned during modem design,and is described in Section 126.96.36.199 of my book. By properly selecting parameters based such analysis, the test network met the original design goal.
In 1992, I moved to Illinois to join the research group at Motorola Corp. Later, I was assigned to lead the development of system simulation for Motorola’s IS-95 mobile device ASIC.
One subject I studied in this project was frequency locked loop (FLL). Because publications on FLLs were relatively scarce, I had to study FLL and derive its system equations from the basics. During the process, I obtained new expressions for the jitter variance at the FLL output. The results on FLL from my study were published in a conference paper in 1996. They are also included in the Chapter 5 of this book.
The system simulation developed from this project was later used as the basis for developing the receiver ASICs used in Motorola IS-95 mobile devices. From its development, I also learned other aspects of carrier synchronization, which are presented in Chapters 4 and 5 of this book.
I found the knowledge that the team lacked was mainly in the synchronization area
In 1996, I moved to Motorola Cellular Infrastructure Group (CIG) working on IS-95 CDMA base station testing, debugging, and implementation. To ensure the acceptable performance of CDMA base-stations, it was necessary to understand their initial acquisition operations, with which I previously was not familiar. Detection and estimation theory was applied to the analysis of initial acquisition in CDMA communication for ensuring required system performance, and the knowledge gained was invaluable for my work later on at Qualcomm in different projects.
In addition, to reduce hardware cost, we developed a digital linear interpolation algorithm, which interpolated Tc/2 samples to samples with an equivalent sampling of T/8, in our receiver ASIC implementation instead of sampling the received signal directly at that rate.
The theory and implementation of initial acquisition are presented in Chapter 3 of this book. The digital interpolation used in CDMA receivers is discussed in Section 188.8.131.52.
In early 1998, I joined Qualcomm Incorporated and started working on the HDR project, which later became the basis of cdma2000 EV-DO, one of the ITU 3G standards. When I joined the project, the staffing was almost complete with the leadership team already in place. I found the knowledge that the team lacked was mainly in the synchronization area. In addition to other technical contributions, I wrote the majority of memos on the analysis, simulation and implementation of synchronization functions in HDR. These memos helped young engineers in development and implementation of the HDR system and its transmitters and receivers.
The APLL and DPLL basics used in the system analysis and prototype development of HDR are described in Chapter 4 of my book. The principles of timing and carrier synchronization and their implementation are covered in Chapters 5 and 6.
From 2003 to 2011, I worked on MediaFLO, the OFDM based mobile television, project, by leading its system, standard and ASIC development efforts.
We worked on various aspects of OFDM communication systems. Related to synchronization, we developed practical channel estimation and timing determination algorithms for the OFDM receiver. These algorithms were thoroughly evaluated through simulation, lab testing and in field trials and achieved the design goals.
The mobile devices based on the receiver ASIC that we developed performed very well in the deployed commercial system. Due to business unviability, the MediaFLO system ceased commercial operation in 2011. However, many of the technologies and algorithms that we developed were employed in other Qualcomm OFDM receiver ASICs. The principles of the synchronization functions for OFDM systems have been presented in the relevant parts of Chapters 5 and 6 in my book.
You can read more about ‘Synchronization in Digital Communiation Systems here.